[PATCH v10 8/9] dt-bindings: add documentation of xilinx clocking wizard
shubhrajyoti.datta at gmail.com
Thu May 13 06:48:09 UTC 2021
On Sat, Apr 10, 2021 at 5:02 AM Stephen Boyd <sboyd at kernel.org> wrote:
> Quoting Michal Simek (2021-04-08 03:40:29)
> > On 4/8/21 12:26 PM, Shubhrajyoti Datta wrote:
> > > On Sun, Mar 7, 2021 at 1:50 AM Rob Herring <robh at kernel.org> wrote:
> > >>
> > >> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> > >>> Add the devicetree binding for the xilinx clocking wizard.
> > >>>
> > >>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta at xilinx.com>
> > >>> ---
> > In designed tools it is your responsibility to select proper chip based
> > on your order and then this value is propagated in Xilinx standard way
> > via device tree generator to fill the right value for this property.
> The OPP framework and binding has support for speed grades via the
> 'supported-hw' property. I expect this speed-grade property could be
> dropped and an opp table could be assigned to the clk controller node
> for this speed grade by the DT author. Unfortunate that it isn't burned
> somewhere into the device so that software can pick the right frequency
> limits that way.
Rob let me know your opinion I will implement it in that way.
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