[PATCH v1 1/1] drm/bridge: anx7625: Tune K value for IVO panel

Xin Ji xji at analogixsemi.com
Fri Aug 6 08:58:29 UTC 2021


On Thu, Aug 05, 2021 at 09:05:29PM +0200, Robert Foss wrote:
> Hey Xin,
> 
> Thanks for submitting this.
> 
> On Thu, 5 Aug 2021 at 09:31, Xin Ji <xji at analogixsemi.com> wrote:
> >
> > IVO panel require less input video clock variation than video clock
> > variation in DP CTS spec.
> >
> > This patch decreases the K value of ANX7625 which will shrink eDP Tx
> > video clock variation to meet IVO panel's requirement.
> >
> > Signed-off-by: Xin Ji <xji at analogixsemi.com>
> > ---
> >  drivers/gpu/drm/bridge/analogix/anx7625.c | 17 ++++++++++++++---
> >  drivers/gpu/drm/bridge/analogix/anx7625.h |  4 +++-
> >  2 files changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > index a3d82377066b..ceed1c7f3f28 100644
> > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > @@ -384,6 +384,18 @@ static int anx7625_odfc_config(struct anx7625_data *ctx,
> >         return ret;
> >  }
> >
> > +static int anx7625_set_k_value(struct anx7625_data *ctx)
> 
> Pardon my ignorance, but I don't know what a K-value is. Could you add
> a comment detailing
> what the K-value does?

Hi Robert Foss, OK, I'll add more comment.
Thanks,
Xin
> 
> > +{
> > +       struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
> > +
> > +       if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
> > +               return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> > +                                        MIPI_DIGITAL_ADJ_1, 0x3B);
> > +
> > +       return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> > +                                MIPI_DIGITAL_ADJ_1, 0x3D);
> > +}
> > +
> >  static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
> >  {
> >         struct device *dev = &ctx->client->dev;
> > @@ -470,9 +482,8 @@ static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
> >                         MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
> >         ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
> >                         (n & 0xff));
> > -       /* Diff */
> > -       ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> > -                       MIPI_DIGITAL_ADJ_1, 0x3D);
> > +       /* Diff and K value */
> 
> With a proper comment above, this comment is no longer needed.
OK
> 
> > +       anx7625_set_k_value(ctx);
> >
> >         ret |= anx7625_odfc_config(ctx, post_divider - 1);
> >
> > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > index 034c3840028f..6dcf64c703f9 100644
> > --- a/drivers/gpu/drm/bridge/analogix/anx7625.h
> > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
> > @@ -210,7 +210,9 @@
> >  #define  MIPI_VIDEO_STABLE_CNT           0x0A
> >
> >  #define  MIPI_LANE_CTRL_10               0x0F
> > -#define  MIPI_DIGITAL_ADJ_1   0x1B
> > +#define  MIPI_DIGITAL_ADJ_1     0x1B
> > +#define  IVO_MID0               0x26
> > +#define  IVO_MID1               0xCF
> >
> >  #define  MIPI_PLL_M_NUM_23_16   0x1E
> >  #define  MIPI_PLL_M_NUM_15_8    0x1F
> > --
> > 2.25.1
> >
> 
> LGTM with the above fix.
> 
> Reviewed-by: Robert Foss <robert.foss at linaro.org>


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