[PATCH v10 8/9] dt-bindings: add documentation of xilinx clocking wizard

Shubhrajyoti Datta shubhrajyoti.datta at gmail.com
Thu Apr 8 10:26:50 UTC 2021


On Sun, Mar 7, 2021 at 1:50 AM Rob Herring <robh at kernel.org> wrote:
>
> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> > Add the devicetree binding for the xilinx clocking wizard.
> >
> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta at xilinx.com>
> > ---
> >  v6:
> >  Fix a yaml warning
> >  v7:
> >  Add vendor prefix speed-grade
> >  v8:
> >  Fix the warnings
> >  v10:
> >  Add nr-outputs
> >
> >  .../bindings/clock/xlnx,clocking-wizard.yaml       | 72 ++++++++++++++++++++++
> >  1 file changed, 72 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> > new file mode 100644
> > index 0000000..280eb09
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Xilinx clocking wizard
> > +
> > +maintainers:
> > +  - Shubhrajyoti Datta <shubhrajyoti.datta at xilinx.com>
> > +
> > +description:
> > +  The clocking wizard is a soft ip clocking block of Xilinx versal. It
> > +  reads required input clock frequencies from the devicetree and acts as clock
> > +  clock output.
> > +
> > +properties:
> > +  compatible:
> > +    const: xlnx,clocking-wizard
>
> Not very specific. Only 1 version of this h/w?

Will fix in next version
>
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: clock input
> > +      - description: axi clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: clk_in1
> > +      - const: s_axi_aclk
> > +
> > +
> > +  xlnx,speed-grade:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [1, 2, 3]
> > +    description:
> > +      Speed grade of the device. Higher the speed grade faster is the FPGA device.
>
> How does one decide what value?
This is a property of the FPGA fabric.
So  hdf/xsa  should tell that
>
> > +
> > +  nr-outputs:
>
> xlnx,nr-outputs
>
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [1, 2, 3, 4, 5, 6, 7, 8]
>
> minimum: 1
> maximum: 8
>
> > +    description:
> > +      Number of outputs.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#clock-cells"
> > +  - clocks
> > +  - clock-names
> > +  - xlnx,speed-grade
> > +  - nr-outputs
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    wizard at b0000000  {
>
> clock-controller at ...
will fix.
>
> > +        compatible = "xlnx,clocking-wizard";
> > +        reg = <0xb0000000 0x10000>;
> > +        #clock-cells = <1>;
> > +        xlnx,speed-grade = <1>;
> > +        nr-outputs = <6>;
> > +        clock-names = "clk_in1", "s_axi_aclk";
> > +        clocks = <&clkc 15>, <&clkc 15>;
> > +    };
> > +...
> > --
> > 2.1.1
> >


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