[PATCH 10/14] ARM: dts: sun8i: v3s: Add MIPI D-PHY and MIPI CSI-2 interface nodes

Paul Kocialkowski paul.kocialkowski at bootlin.com
Fri Oct 23 17:45:42 UTC 2020


MIPI CSI-2 is supported on the V3s with an A31 controller, which seems
to be used on all Allwinner chips supporting it, except for the A83T.
The controller is connected to CSI0 through fwnode endpoints.
The mipi_csi2_in port node is provided to connect MIPI CSI-2 sensors.

The D-PHY part is the same that already drives DSI, but used in Rx mode.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski at bootlin.com>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 50 ++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 07722bc5df11..6e10c10ab283 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -534,6 +534,13 @@ csi0: camera at 1cb0000 {
 			clock-names = "bus", "mod", "ram";
 			resets = <&ccu RST_BUS_CSI>;
 			status = "disabled";
+
+			csi0_in: port {
+				csi0_in_mipi_csi2: endpoint {
+					bus-type = <4>; /* CSI2_DPHY */
+					remote-endpoint = <&mipi_csi2_out_csi0>;
+				};
+			};
 		};
 
 		csi1: camera at 1cb4000 {
@@ -558,5 +565,48 @@ gic: interrupt-controller at 1c81000 {
 			#interrupt-cells = <3>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
+
+		mipi_csi2: mipi-csi2 at 1cb1000 {
+			compatible = "allwinner,sun8i-v3s-mipi-csi2",
+				     "allwinner,sun6i-a31-mipi-csi2";
+			reg = <0x01cb1000 0x1000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CSI>,
+				 <&ccu CLK_CSI1_SCLK>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_CSI>;
+			status = "disabled";
+
+			phys = <&dphy>;
+			phy-names = "dphy";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mipi_csi2_in: port at 0 {
+					reg = <0>;
+				};
+
+				mipi_csi2_out: port at 1 {
+					reg = <1>;
+
+					mipi_csi2_out_csi0: endpoint {
+						remote-endpoint = <&csi0_in_mipi_csi2>;
+					};
+				};
+			};
+		};
+
+		dphy: d-phy at 1cb2000 {
+			compatible = "allwinner,sun6i-a31-mipi-dphy";
+			reg = <0x01cb2000 0x1000>;
+			clocks = <&ccu CLK_BUS_CSI>,
+				 <&ccu CLK_MIPI_CSI>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_CSI>;
+			status = "disabled";
+			#phy-cells = <0>;
+		};
 	};
 };
-- 
2.28.0



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