[PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

[Sergio Paracuellos]

Hi Chuanhong,

On Thu, Nov 12, 2020 at 2:26 AM Chuanhong Guo <gch981213 at gmail.com> wrote:
[snip]
>
> I've already said in previous threads that clock assignment in
> current linux kernel is not trustworthy.
> I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> Most of your clock assumptions above are incorrect.

Well, that was of course expected, without a real clock plan this
driver was only taking into account Oleksij Rempel suggestions to try
to make a driver good enough to properly be maintained :).

> I've made a clock driver with gate support a few months ago.[0]
> but I don't have much time to really finish it.
> Maybe you could rework your clock gate driver based on it.
>
> [0] https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133

Thanks for the link, I see there are three more clocks there with
frequencies of 125, 250 and 270 Mhz. all of them having main xtal as
parent. Ok, I will take this real information into account and will
send v2 after a bit of more feedback comes.

> --
> Regards,
> Chuanhong Guo

Best regards,
     Sergio Paracuellos