[PATCH] staging: mt7621-dts: fix PCIe interrupt mapping
Sergio Paracuellos
sergio.paracuellos at gmail.com
Sun Apr 12 10:29:26 UTC 2020
MT7621 has three assigned interrupts for the pcie. This
interrupts should properly being mapped taking into account
which devices are finally connected in which bus. Because of
this current information of these mappings is not enough and
should be a little modified to properly got interrupts working
for any scenario. For example, as it is now, if we only have
connected pcie1 on PCI enumeration will get that bus 1 is using
slot 0 for this pci device and the interrupt will be wrongly
mapped to the one in pcie0 istead of use the good one for pcie1.
Hence, add interrupt map information to pcie child nodes and
properly update the global pcie node information.
Fixes: 46d093124df4 ("staging: mt7621-pci: improve interrupt mapping")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos at gmail.com>
---
Tested in gnubee pc1 (which uses all the buses and also worked without
changes) and tested also in ZyXEL LTE3301-PLUS which has PCIe and a
mt7615e connected to second bus on the first phy where the current
mapping was failing and this changes seems to fix the mapping problems.
On gnubee we get:
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
...
23: 0 0 0 0 MIPS GIC 11 ahci[0000:01:00.0]
24: 0 0 0 0 MIPS GIC 31 ahci[0000:02:00.0]
25: 279 0 0 0 MIPS GIC 32 ahci[0000:03:00.0]
On the ZyXEL LTE3301-PLUS before this changes (wrongly '23' (pcie0 one) is assigned):
root at OpenWrt:/# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
...
23: 0 0 0 0 MIPS GIC 11 mt7615e
After this changes:
root at OpenWrt:/# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
...
24: 85 0 0 0 MIPS GIC 31 mt7615e
Thanks!
drivers/staging/mt7621-dts/mt7621.dtsi | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 9e5cf68731bb..bee7731eb60a 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -524,10 +524,10 @@ pcie: pcie at 1e140000 {
>;
#interrupt-cells = <1>;
- interrupt-map-mask = <0xF0000 0 0 1>;
- interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
- <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
- <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xF800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -544,6 +544,9 @@ pcie at 0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
ranges;
bus-range = <0x00 0xff>;
};
@@ -552,6 +555,9 @@ pcie at 1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
ranges;
bus-range = <0x00 0xff>;
};
@@ -560,6 +566,9 @@ pcie at 2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
ranges;
bus-range = <0x00 0xff>;
};
--
2.25.1
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