staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

Greg Ungerer gerg at kernel.org
Fri May 31 12:47:07 UTC 2019


Hi Sergio,

On 31/5/19 10:37 pm, Sergio Paracuellos wrote:
> On Thu, May 30, 2019 at 3:46 AM Greg Ungerer <gerg at kernel.org> wrote:
>> On 30/5/19 10:44 am, Greg Ungerer wrote:
>>> On 29/5/19 6:08 pm, Sergio Paracuellos wrote:
>>> [snip]
>>>> I have added gpio consumer stuff and reorder a bit the code to be more
>>>> similar to 4.20.
>>>>
>>>> I attach the patch. I have not try it to compile it, because my normal
>>>> environment is in another
>>>> computer and I am in the middle of moving from my current house and
>>>> don't have access to it, sorry.
>>>> So, please try this and let's see what happens.
>>>
>>> No problem, thanks for the patch.
>>>
>>> Unfortunately always locks up on kernel boot:
>>>
>>>     ...
>>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
>>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
>>>     mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
>>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
>>>     mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
>>>     mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
>>>     mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
>>>
>>> That was original linux-5.1 patched with your attached patch.
>>>
>>> I'll try and dig down into that further today and get some
>>> feedback on where it is failing.
>>
>> The first problem I see is that the GPIO MODE register bits for
>> PERST_MODE are set to 00, so in "PCIe Reset" mode. If I hack in
>> a register update for that with:
>>
>>       /* Force PERST PCIe reset into GPIO mode */
>>       *(unsigned int *)(0xbe000060) |=  BIT(10);
> 
> I have set GPIO mode for this in the new attached patch.
> 
>>
>> I do that at the start of mt7621_pcie_init_ports(). With that in
>> place I get further:
>>
>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
>>     mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
>>     mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
>>     mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
>>     mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
>>     mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
>>     mt7621-pci 1e140000.pcie: PCIE0 enabled
>>     mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
>>     mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
>>     pci_bus 0000:00: root bus resource [io  0xffffffff]
>>     pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
>>     pci_bus 0000:00: root bus resource [bus 00-ff]
>>     pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
>>
>> It hangs there...
> 
> I had review the boot order is working for you in version 4.20 and the
> order with the new patch applied. There were
> only one difference, the place where interrupt bits are set. I have
> changed that also in the new attached patch.
> 
> For me, the order now and how the different boot steps are being done
> in v4.20 are the same.
> 
> One other thing I don't really understand why is needed but is in the
> v4.20 code are this two lines:
> 
> pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
> pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
> 
> These are added also in the current patch.

Thats great, thanks for your efforts on this.
I will try first thing Monday morning my time and get back to you.

Regards
Greg



>> Regards
>> Greg
> 
> Hope this helps.
> 
> Best regards,
>      Sergio Paracuellos
>>
>>


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