staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

Greg Ungerer gerg at kernel.org
Thu May 30 00:47:22 UTC 2019


Hi Brett,

On 30/5/19 12:44 am, Brett Neumeier wrote:
> On Wed, May 29, 2019 at 3:09 AM Sergio Paracuellos <sergio.paracuellos at gmail.com <mailto:sergio.paracuellos at gmail.com>> wrote:
> 
>     I have added gpio consumer stuff and reorder a bit the code to be more
>     similar to 4.20.
> 
>     I attach the patch. I have not try it to compile it, because my normal
>     environment is in another
>     computer and I am in the middle of moving from my current house and
>     don't have access to it, sorry.
>     So, please try this and let's see what happens.
> 
> I'm jumping in late here because I just recently became aware of this thread. I have a GnuBee PC2 on which I'm running a 5.1.4 kernel with Neil Brown's patches applied; I'm having an issue where approximately 2/3 of the time the kernel hangs from a cold boot while configuring PCIe. I'd be happy to test whatever patches might help disagnose or correct what's going on. (I am not an expert device driver engineer or anything, so I probably won't be much help in other ways.)
> 
> In case it is helpful -- the kernel messages logged regardless of whether or not the problem occurs are:
> 
> mt7621-pci 1e140000.pcie: Parsing DT failed
> mt7621_gpio 1e000600.gpio: registering 32 gpios
> mt7621_gpio 1e000600.gpio: registering 32 gpios
> mt7621_gpio 1e000600.gpio: registering 32 gpios
> spi-mt7621 1e000b00.spi: sys_freq: 225000000
> rt2880-pinmux pinctrl: pcie is already enabled
> mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> mt7621-pci 1e140000.pcie: PCIE0 enabled
> mt7621-pci 1e140000.pcie: PCIE0 enabled
> mt7621-pci 1e140000.pcie: PCIE0 enabled
> mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [io  0xffffffff]
> pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> pci_bus 0000:00: root bus resource [bus 00-ff]
> pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> 
> at that point the boot process sometimes hangs.

FWIW, I see this occasional hang here too. Sometimes it boots through,
sometimes hangs - with unchanged code.

Difference is when I get a good boot, I never get the PCI bus
probed, and never any devices found.

Regards
Greg


> When it does not hang, it proceeds with:
> 
> pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> 
> and then does a bunch of resource assignments and things and all is well.
> 
> I'm building a new kernel with the "use perst gpio instead of builtin perst" patch and will report back my results. If there's anything else I can do to help, please let me know!
> 
> -- 
> Brett Neumeier (bneumeier at gmail.com <mailto:bneumeier at gmail.com>)


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