[PATCH 1/3] staging: mt7621-dts: simplify pcie phy bindings
Sergio Paracuellos
sergio.paracuellos at gmail.com
Fri Mar 29 05:54:05 UTC 2019
Hi Neil,
Thanks for the feedback.
On Fri, Mar 29, 2019 at 4:01 AM NeilBrown <neil at brown.name> wrote:
>
> On Thu, Mar 28 2019, Sergio Paracuellos wrote:
>
> > If each phy port doesn't have its own resources, then we don't need
> > child nodes. Handle it using #phy-cells to 1 or 0 conveniently.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos at gmail.com>
> > ---
> > drivers/staging/mt7621-dts/mt7621.dtsi | 23 +++--------------------
> > 1 file changed, 3 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> > index 17020e24abd2..7a85d8b086bb 100644
> > --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> > +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> > @@ -491,7 +491,7 @@
> > reset-names = "pcie", "pcie0", "pcie1", "pcie2";
> > clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> > clock-names = "pcie0", "pcie1", "pcie2";
> > - phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
> > + phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy>;
>
> I would be more comfortable if this was
>
> phys = <&pcie0_phy 0>, <&pcie0_phy 1>, <&pcie1_phy 0>;
>
> and pcie-phy at 1 had #phy-cells = <1>;
Yes, maybe is more clear when looking at the phy client bindings.
Changed in v2.
>
> Thanks,
> NeilBrown
Best regards,
Sergio Paracuellos
>
> > phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> >
> > pcie at 0,0 {
> > @@ -522,29 +522,12 @@
> > pcie0_phy: pcie-phy at 1e149000 {
> > compatible = "mediatek,mt7621-pci-phy";
> > reg = <0x1e149000 0x0700>;
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > -
> > - pcie0_port: pcie-phy at 0 {
> > - reg = <0>;
> > - #phy-cells = <0>;
> > - };
> > -
> > - pcie1_port: pcie-phy at 1 {
> > - reg = <1>;
> > - #phy-cells = <0>;
> > - };
> > + #phy-cells = <1>;
> > };
> >
> > pcie1_phy: pcie-phy at 1e14a000 {
> > compatible = "mediatek,mt7621-pci-phy";
> > reg = <0x1e14a000 0x0700>;
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > -
> > - pcie2_port: pcie-phy at 0 {
> > - reg = <0>;
> > - #phy-cells = <0>;
> > - };
> > + #phy-cells = <0>;
> > };
> > };
> > --
> > 2.19.1
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