[PATCH 19/22] staging: comedi: adv_pci1710: fix counter 0 internal clock source

[Hartley Sweeten]

On Friday, November 06, 2015 10:22 AM, Ian Abbott wrote:
> Just so we're on the same page, I downloaded the user manual from
> http://support.advantech.com/support/SearchResult.aspx?keyword=PCI-1710&searchtabs=Manual
>
> Strangely, the date on the download page is 2015-10-28 which seems a bit 
> recent, although the actual vintage seems to be 2nd Edition, November 2003.

<snip>

> In the manual I have, section "A.1 PCI-1710/1710L/1710HG/1710HGL" has 
> channel 2 taking its input from the output of channel 1, channel 1 using 
> a 1 MHz clock, channel 0 Internal 100 kHz or external (1 MHz) max.
>
> Section "A.2 PCI-1711/1711L Specifications" has channel 2 taking the 
> output of 1, channel 1 using 1 MHz, and channel 0 Internal 1 MHz or 
> external (10 MHz) max.
>
> Section "A.3 PCI-1716/1716L Specifications" has same counter spec as 
> PCI-1711.

<snip>

> I can't see a block diagram, but "Table 3-1 I/O Connector Signal 
> Description" says:
>
> Counter 0 Clock Input. The clock input of counter 0 can be
> either external (up to 10 MHz) or internal (1 MHz), as set by
> software.

<snip>

> In the manual I have, section "3.5 Trigger Source Connections" says they 
> are connected to a 10 MHz clock.

<snip>

> In the manual I have, section "C.7 Control Register - BASE+6" says:
>
> CNT0	Counter 0 clock source select bit
>	0	The clock source of Counter 0 comes from the
>		internal clock
>		1 MHz for PCI-1711/1711L/17161716L
>		100 KHz for PCI-1710/1710L/1710HG/
>		1710HGL
>	1	The clock source of Counter 0 comes from the
>		external clock
>		maximum up to 10 MHz for PCI-1711/1711L/
>		1716/1716L
>		maximum up to 1 MHz for PCI-1710/1710L/
>		1710HG/1710HGL

<snip>

> I agree the manuals are a bit messed up!

Ian,

This is a mess...

There are block diagrams in this manual:
http://downloadt.advantech.com/ProductFile/Downloadfile1/1-11P65IP/PCI-1710.pdf

The PCI-1710/1710L/1710HF/1710HGL show a  1MHz clock to Counter 1 (cascading to
Counter 2) and a 1 MHz/10 (100 kHz) or external clock to Counter 0.

The PCI-1711/1711L shows a 10 MHz clock to Counter 1 (cascaded to counter 2) and
a 10 MHz/10 (1 MHz) or external clock to Counter 0. The PCI-1716/1716L (not currently
supported by the driver) shows the same clock sources.

The PC-1710U manual shows the same 1 MHz and 1 MHz/10 clocks:
http://downloadt.advantech.com/ProductFile/Downloadfile1/1-11P65IR/PCI-1710U.pdf

I have another manual for the PCI-1710/1710HG and it shows a 10 MHz clock to Counter
1 (cascaded to Counter 2) and a 10 MHz/10 (1 MHz) or external clock to Counter 0.

The other PCI-1711U series manual I have also shows the 10 MHz and 10MHz/10 clocks.

The PCI-1713 manual shows the same 10MHz clock for the pacer. But I just noticed that
it does not provide the external signals for Counter 0. Need to fix that patch....

Logically I think the 10 MHz base clock for the pacer and 1 MHz internal clock for the user
counter make more sense. With all the manual issues and without the actual hardware
there is no way to verify what is really correct.

Hartley