[PATCH 18/66] staging: comedi: pcl818: fix PCL818_FI_DATAHI

[Ian Abbott]

On 2014-03-03 16:00, Ian Abbott wrote:
> On 2014-02-28 23:24, H Hartley Sweeten wrote:
>> The A/D FIFO uses two registers to get each analog data sample.
>> PCL818_FI_DATALO is the LSB of the data and PCL818_FI_DATAHI is
>> the MSB of the data. The current define for PCL818_FI_DATAHI is
>> incorrect and results in the LSB getting read twice.
>
> Well caught!  That's one for my list of stable backport patches!
>

However, that still leaves the question of when the FIFO read position 
is advanced.  If reading the DATAHI register advances the FIFO, 
presumably the original code never advances the FIFO, but if reading the 
DATALO register advances the FIFO, the original code would advance it 
twice as fast as it should be.

The user manual doesn't actually say which register advances the FIFO, 
but I found some MS-DOS code on the Advantech site (DIRECT.IO/C/FIFO.C 
in PCL818HG.150.zip) that reads it LO then HI, so I guess reading the HI 
register advances the FIFO.

-- 
-=( Ian Abbott @ MEV Ltd.    E-mail: <abbotti at mev.co.uk>        )=-
-=( Tel: +44 (0)161 477 1898   FAX: +44 (0)161 718 3587         )=-