[PATCH] staging: gs_fpgaboot: add bus_width module parameter

Cihangir Akturk cakturk at gmail.com
Fri Aug 22 23:09:40 UTC 2014


On Fri, Aug 22, 2014 at 11:14:09AM -0500, Greg KH wrote:
> On Fri, Aug 22, 2014 at 02:16:02PM +0300, Cihangir Akturk wrote:
> > This parameter allows the program bus width to be specified at
> > module insertion time.
> 
> Why?  Who would set this?  Why is it a module option and not a device
> option?  Adding module options is frowned apon if at all possible.

When I read the following line [1] in the TODO file, I thought the
solution for this was a simple module parameter, which obviously was
wrong.

Actually I don't know much about the programming process of a FPGA,
but after reading the Xilinx App notes, It has become clear that
this has nothing to do with the aformentioned TODO entry.

Apologize for the inconvenience. Please ignore this patch.

 [1] "get bus width input instead of hardcoded bus width"

thanks,

cihangir


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