[PATCH] Staging: bcm: DDRInit: fixed comment issues.
Gary Rookard
garyrookard at gmail.com
Fri Dec 13 15:02:11 UTC 2013
replaced C99 style with C89 standard style comments
to follow the linux kernel coding style thus fixing
checkpatch errors respectfully.
also, in some instances changed comments from inline
to side-bar style.
Signed-off-by: Gary Alan Rookard <garyrookard at gmail.com>
---
On branch staging-next
drivers/staging/bcm/DDRInit.c | 315 ++++++++++++++++++------------------------
1 file changed, 137 insertions(+), 178 deletions(-)
diff --git a/drivers/staging/bcm/DDRInit.c b/drivers/staging/bcm/DDRInit.c
index 939fe73..41132b5 100644
--- a/drivers/staging/bcm/DDRInit.c
+++ b/drivers/staging/bcm/DDRInit.c
@@ -5,41 +5,39 @@
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820
- //DDR INIT-133Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 //index for 0x0F007000
-static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {// # DPLL Clock Setting
+/* DDR INIT-133Mhz */
+#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = { /* DPLL Clock Setting */
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF1B00},
+ {0x0f000840, 0x0FFF1B00}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020001}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
- {0x0F00702c, 0x0206060a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0206060a}, /* ROB - 0x0205050a,0x0206060a */
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
- {0x0F007038, 0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x02101010},//ROB - 0x02101010,//0x02101018},
- {0x0F007040, 0x45751200},//ROB - 0x45751200,//0x450f1200},
- {0x0F007044, 0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x110a0200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x02101010}, /* ROB - 0x02101010,0x02101018}, */
+ {0x0F007040, 0x45751200}, /* ROB - 0x45751200,0x450f1200}, */
+ {0x0F007044, 0x110a0d00}, /* ROB - 0x110a0d00//0x111f0d00 */
{0x0F007048, 0x081b0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
@@ -56,16 +54,13 @@ static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {// # DPLL Clock Se
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F007094, 0x00000104}, /* Enable BW improvement within memory controller */
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-bar */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-//80Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 //index for 0x0F007000
-static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {// # DPLL Clock Setting
+/* 80Mhz-T3 */
+#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07f1ffff},
{0x0f000860, 0x00000000},
@@ -76,8 +71,7 @@ static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {// # DPLL Clock Settin
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
{0x0F00a04C, 0x0000000C},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
@@ -112,38 +106,34 @@ static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {// # DPLL Clock Settin
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-//100Mhz
-#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 //index for 0x0F007000
-static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {// # DPLL Clock Setting
+/* 100Mhz-T3 */
+#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = { /* DPLL Clock Setting */
{0x0F000800, 0x00007008},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13E3F},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- //0x0f000840,0x0FFF1800,
- {0x0f000840, 0x0FFF1B00},
+ /* 0x0f000840,0x0FFF1800, */
+ {0x0f000840, 0x0FFF1B00}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-barv */
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001}, // POP - 0x00020000 Normal 0x01020000
- {0x0F007020, 0x04020107},//Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020001}, /* POP - 0x00020000 Normal - 0x01020000 */
+ {0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
@@ -153,7 +143,7 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {// # DPLL Clock Settin
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
- {0x0F007048, 0x06120305},//0x02690204 // 0x06120305
+ {0x0F007048, 0x06120305}, /* 0x02690204 0x06120305 */
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001C},
{0x0F007054, 0x00000000},
@@ -169,61 +159,54 @@ static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {// # DPLL Clock Settin
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F007094, 0x00000104}, /* Enable BW improvement within memory controller */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-//Net T3B DDR Settings
-//DDR INIT-133Mhz
+/* Net T3B DDR Settings */
+/* DDR INIT-133Mhz */
static struct bcm_ddr_setting asDPLL_266MHZ[] = {
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF1B00},
+ {0x0f000840, 0x0FFF1B00}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000870, 0x00000002}
};
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 //index for 0x0F007000
-static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
+#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13652},
{0x0f000840, 0x0FFF0800},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000880, 0x000003DD},
+ {0x0f000880, 0x000003DD}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000860, 0x00000000},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0F00a044, 0x1fffffff},
+ {0x0F00a044, 0x1fffffff}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-bar */
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020001}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
- {0x0F00702c, 0x0206060a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0206060a}, /* ROB - 0x0205050a,//0x0206060a */
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
- {0x0F007038, 0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x02101012},//ROB - 0x02101010,//0x02101018},
- {0x0F007040, 0x457D1200},//ROB - 0x45751200,//0x450f1200},
- {0x0F007044, 0x11130d00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x130a0200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x02101012}, /* ROB - 0x02101010,0x02101018}, */
+ {0x0F007040, 0x457D1200}, /* ROB - 0x45751200,0x450f1200}, */
+ {0x0F007044, 0x11130d00}, /* ROB - 0x110a0d00 0x111f0d00 */
{0x0F007048, 0x040D0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
@@ -240,14 +223,12 @@ static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {// # DPLL Clock S
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000},
+ {0x0F007094, 0x00000104}, /* Enable BW improvement within memory controller */
+ {0x0F007018, 0x01010000}, /* Enable start bit within memory controller */
};
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
-static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
+#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13FFF},
{0x0f000840, 0x0FFF1F00},
@@ -259,8 +240,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {// # DPLL Clock S
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
@@ -295,13 +275,12 @@ static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {// # DPLL Clock S
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-//100Mhz
-#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 //index for 0x0F007000
-static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
+/* 100MHz-T3B */
+#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F1369B},
{0x0f000840, 0x0FFF0800},
@@ -311,18 +290,16 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {// # DPLL Clock S
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-bar */
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000}, // POP - 0x00020000 Normal 0x01020000
- {0x0F007020, 0x04020107},//Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020000}, /* POP - 0x00020000 Normal - 0x01020000 */
+ {0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
@@ -332,7 +309,7 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {// # DPLL Clock S
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
- {0x0F007048, 0x06120305},//0x02690204 // 0x06120305
+ {0x0F007048, 0x06120305}, /* 0x02690204 0x06120305 */
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001C},
{0x0F007054, 0x00000000},
@@ -348,45 +325,41 @@ static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {// # DPLL Clock S
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00000104},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F007094, 0x00000104}, /* Enable BW improvement within memory controller */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {// # DPLL Clock Setting
+#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = { /* DPLL Clock Setting */
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
+ {0x0f000840, 0x0FFF0000}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020001}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
- {0x0F00702c, 0x0206060a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0206060a}, /* ROB- 0x0205050a,0x0206060a */
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
- {0x0F007038, 0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x02101020},//ROB - 0x02101010,//0x02101018,
- {0x0F007040, 0x45711200},//ROB - 0x45751200,//0x450f1200,
- {0x0F007044, 0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x200a0200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x02101020}, /* ROB - 0x02101010,0x02101018, */
+ {0x0F007040, 0x45711200}, /* ROB - 0x45751200,0x450f1200, */
+ {0x0F007044, 0x110D0D00}, /*vROB - 0x110a0d00 0x111f0d00 */
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
@@ -406,47 +379,43 @@ static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {// # DPLL Clock Setti
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00040000},
+ {0x0F007094, 0x00040000}, /* Enable BW improvement within memory controller */
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
- //# Enable 2 ports within X-bar
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ /* Enable 2 ports within X-bar */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {// # DPLL Clock Setting
+/* 100MHz-T3LP */
+#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
+ {0x0f000840, 0x0FFF0000}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04020107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020000}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
- {0x0F00702c, 0x0204040a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0204040a}, /* ROB- 0x0205050a,0x0206060a */
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
- {0x0F007038, 0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x0203031F},//ROB - 0x02101010,//0x02101018,
- {0x0F007040, 0x6e001200},//ROB - 0x45751200,//0x450f1200,
- {0x0F007044, 0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x1F080200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x0203031F}, /* ROB - 0x02101010,0x02101018, */
+ {0x0F007040, 0x6e001200}, /* ROB - 0x45751200,0x450f1200, */
+ {0x0F007044, 0x011a0a00}, /* ROB - 0x110a0d00 0x111f0d00 */
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
@@ -469,14 +438,12 @@ static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {// # DPLL Clock Setti
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-bar */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {// # DPLL Clock Setting
+#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = { /* DPLL Clock Setting */
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
@@ -533,10 +500,10 @@ static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {// # DPLL Clock Settin
-///T3 LP-B (UMA-B)
+/* T3 LP-B (UMA-B) */
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {// # DPLL Clock Setting
+#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = { /* DPLL Clock Setting */
{0x0f000820, 0x03F137DB},
{0x0f000810, 0x01842795},
{0x0f000860, 0x00000000},
@@ -544,8 +511,8 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {// # DPLL Clock Sett
{0x0f000840, 0x0FFF0400},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
- {0x0F00a084, 0x1Cffffff},//Now dump from her in internal memory
+ {0x0f003050, 0x00000021}, /* this is flash/eeprom clock divisor which set the flash clock to 20 MHz */
+ {0x0F00a084, 0x1Cffffff}, /* Now dump from her in internal memory */
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
@@ -592,39 +559,37 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {// # DPLL Clock Sett
};
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {// # DPLL Clock Setting
+#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = { /* DPLL Clock Setting */
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
+ {0x0f000840, 0x0FFF0000}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
- {0x0F00a084, 0x1Cffffff},//dump from here in internal memory
+ {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
+ {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020001},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04030107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020001}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04030107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
- {0x0F00702c, 0x0206060a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0206060a}, /* ROB- 0x0205050a,0x0206060a */
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
- {0x0F007038, 0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x02101017},//ROB - 0x02101010,//0x02101018,
- {0x0F007040, 0x45171200},//ROB - 0x45751200,//0x450f1200,
- {0x0F007044, 0x11290D00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x190a0200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x02101017}, /* ROB - 0x02101010,0x02101018, */
+ {0x0F007040, 0x45171200}, /* ROB - 0x45751200,0x450f1200, */
+ {0x0F007044, 0x11290D00}, /* ROB - 0x110a0d00//0x111f0d00 */
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
@@ -644,48 +609,44 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {// # DPLL Clock Sett
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
- //# Enable BW improvement within memory controller
- {0x0F007094, 0x00040000},
+ {0x0F007094, 0x00040000}, /* Enable BW improvement within memory controller */
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
- //# Enable 2 ports within X-bar
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ /* Enable 2 ports within X-bar */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {// # DPLL Clock Setting
+#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = { /* DPLL Clock Setting */
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
- // Changed source for X-bar and MIPS clock to APLL
- {0x0f000840, 0x0FFF0000},
+ {0x0f000840, 0x0FFF0000}, /* Changed source for X-bar and MIPS clock to APLL */
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
- {0x0F00a084, 0x1Cffffff}, //dump from here in internal memory
+ {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
+ {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
{0x0F00a080, 0x1C000000},
- //Memcontroller Default values
- {0x0F007000, 0x00010001},
+ {0x0F007000, 0x00010001}, /* Memcontroller Default values */
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
- {0x0F00701c, 0x01020000},// POP - 0x00020001 Normal 0x01020001
- {0x0F007020, 0x04020107}, //Normal - 0x04030107 POP - 0x05030107
+ {0x0F00701c, 0x01020000}, /* POP - 0x00020001 Normal - 0x01020001 */
+ {0x0F007020, 0x04020107}, /* Normal - 0x04030107 POP - 0x05030107 */
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
- {0x0F00702c, 0x0204040a},//ROB- 0x0205050a,//0x0206060a
+ {0x0F00702c, 0x0204040a}, /* ROB- 0x0205050a,//0x0206060a */
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
- {0x0F007038, 0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
- {0x0F00703C, 0x0203031F},//ROB - 0x02101010,//0x02101018,
- {0x0F007040, 0x6e001200},//ROB - 0x45751200,//0x450f1200,
- {0x0F007044, 0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
+ {0x0F007038, 0x1F080200}, /* ROB - 0x110a0200,0x180a0200, 0x1f0a0200 */
+ {0x0F00703C, 0x0203031F}, /* ROB - 0x02101010,0x02101018, */
+ {0x0F007040, 0x6e001200}, /* ROB - 0x45751200,0x450f1200, */
+ {0x0F007044, 0x011a0a00}, /* ROB - 0x110a0d00 0x111f0d00 */
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
@@ -708,14 +669,12 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {// # DPLL Clock Sett
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
- //# Enable 2 ports within X-bar
- {0x0F00A000, 0x00000016},
- //# Enable start bit within memory controller
- {0x0F007018, 0x01010000}
+ {0x0F00A000, 0x00000016}, /* Enable 2 ports within X-bar */
+ {0x0F007018, 0x01010000} /* Enable start bit within memory controller */
};
-#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 //index for 0x0F007000
-static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[] = {// # DPLL Clock Setting
+#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 /* index for 0x0F007000 */
+static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[] = { /* DPLL Clock Setting */
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
@@ -723,8 +682,8 @@ static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[] = {// # DPLL Clock Setti
{0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
- {0x0f003050, 0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
- {0x0F00a084, 0x1Cffffff},// dump from here in internal memory
+ {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor which set the flash clock to 20 MHz */
+ {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
@@ -924,7 +883,7 @@ int ddr_init(struct bcm_mini_adapter *Adapter)
break;
case DDR_133_MHZ:
- if (Adapter->bDPLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
+ if (Adapter->bDPLLConfig == PLL_266_MHZ) /* 266Mhz PLL selected. */
{
memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
sizeof(asDPLL_266MHZ));
@@ -1229,7 +1188,7 @@ int download_ddr_settings(struct bcm_mini_adapter *Adapter)
default:
return -EINVAL;
}
- //total number of Register that has to be dumped
+ /* total number of Register that has to be dumped */
value = RegCount;
retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
if (retval)
@@ -1239,7 +1198,7 @@ int download_ddr_settings(struct bcm_mini_adapter *Adapter)
return retval;
}
ul_ddr_setting_load_addr += sizeof(ULONG);
- /*signature */
+ /* signature */
value = (0x1d1e0dd0);
retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
if (retval)
--
1.8.4
More information about the devel
mailing list