Altera's FPGA PCIe chaining DMA example IP core
leon.woestenberg at gmail.com
Mon Aug 18 19:44:17 UTC 2008
On Fri, Aug 15, 2008 at 12:20 AM, Greg KH <greg at kroah.com> wrote:
> On Mon, Aug 04, 2008 at 12:00:58AM +0200, Leon Woestenberg wrote:
>> Hello all,
>> there exist an increasing number of default FPGA IP cores with a
>> scatter/gather DMA controller, either as a silicon core or
>> programmable logic core.
>> In case of Altera, there exist an example chaining DMA IP core that
>> can use the soft or hard IP core and provided a clean host-memory
>> descriptor based approach to scatter/gather DMA. It acts as a starting
>> point for customization.
>> I would like to see if there is interest in developing a clean Linux
>> driver counterpart.
> What could such a driver be used for? It seems that this device is a
> building block for other hardware types, right?
Yes, with the major FPGA vendors now laying the full PCIe stack in
silicon, together with the Phy which is using the high speed on-chip
tranceiver, FPGA's have become a cheap PCIe solution.
It interfaces with higher layers (on the FPGA logic) either with
address/data buses or with FIFO's, which then quickly becomes
application dependent. Inbetween the FPGA vendors typically provide an
example DMA state machine. In my specific case it supports chaining or
I would like to build a reference driver that foresees in driving that
Yes it would be a building block.
It would be a common ground, or reference driver which is only
complete in the sense that it can perform scatter/gather DMA from
small on-FPGA memory to/from host (aka root complex) memory.
If this is OK I would like to perform the project management myself,
in the worst case it would be a single-person effort, but at least
it's in the open.
I have subscribed to the project ml and will re-post the proposal with
a few more links to the documentation.
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