Altera's FPGA PCIe chaining DMA example IP core

Leon Woestenberg leon.woestenberg at
Sun Aug 3 22:00:58 UTC 2008

Hello all,

there exist an increasing number of default FPGA IP cores with a
scatter/gather DMA controller, either as a silicon core or
programmable logic core.

In case of Altera, there exist an example chaining DMA IP core that
can use the soft or hard IP core and provided a clean host-memory
descriptor based approach to scatter/gather DMA. It acts as a starting
point for customization.

I would like to see if there is interest in developing a clean Linux
driver counterpart.

I can spend time on this, and I will. But I'm sure this can proceed
faster in a joint effort.

In any case, I'll like to ask if this is the right mailing list to ask
for advice on device driver internals.


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